There is a current interest in CMOS active pixel imagers for possible use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. FIG. 1 illustrates an exemplary pixel 4T cell 10 in an image sensor 5, where “4T” designates the use of four transistors to operate the pixel 10 as is commonly understood in the art. A 4T pixel has a photodiode 12, a transfer transistor a reset transistor 13, a source follower transistor 14, and a row select transistor 15. It should be understood that FIG. 1 shows the circuitry for the operation of a single pixel, and that in practical use there will be an M-by-N array of identical pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodiode 12 converts incident photons to electrons that are transferred to a storage node FD through transfer transistor 11. A source follower transistor 14 has its gate connected to node FD and amplifies the signal appearing at node FD. When a particular row containing pixel 10 is selected by the row select transistor 15, the signal amplified by transistor 14 is passed to a column line 17 to the readout circuitry. The photodiode 12 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager 5 might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 13 to node FD. The gate of transfer transistor 11 is coupled to a transfer control line which serves to control the transfer operation by which photodiode 12 is connected to node FD. The gate of reset transistor 13 is coupled to a reset control line, which serves to control the reset operation in which Vrst is connected to node FD. The row select control line is typically coupled to all of the pixels of the same row of the array. A supply voltage source is coupled to the source follower transistor 14. Although not shown in FIG. 1, column line 17 is coupled to all of the pixels of the same column of the array and typically has a current sink transistor 16 at one end. The gate of row select transistor 15 is coupled to row select control line.
As known in the art, a value is read from pixel 5 using a two-step process. During a reset period, node FD is reset by turning on reset transistor 13, and the reset voltage is applied to node FD and read out to column line 17 by the source follower transistor 14 (through the activated row select transistor 15). During a charge integration period the photodiode 12 converts photons to electrons. After the integration period the transfer transistor 11 is then activated, allowing the electrons from photodiode 12 to collect at node FD. The charges at node FD are amplified by source follower transistor 14 and selectively passed to column line 17 by row access transistor 15. As a result, the two different values—the reset voltage (Vrst) and the image signal voltage (Vsig)—are readout from the pixel 10 and sent by the column line 17 to readout circuitry, where each voltage is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column lines 17 and stored in respective sample and hold circuits. Then the column circuitry in the sample and hold circuits are activated for reset and signal voltage readout processing.
Typically, pixel readout has been accomplished with source follower transistor 14 in the pixel 10, selectable by row select transistor 15. This source follower transistor 14 has a gain less then unity (˜0.8) due to the finite output impedance of the source follower transistor 14 and current sink transistor 16. In addition, the source follower transistor 14 is typically an N channel transistor in a grounded substrate, resulting in a gain non-linearity over the signal range due to back-gate bias (also known as body effect or bulk effect). Process variations can also cause a slightly different gain from one pixel to another. This combined with the non-linearity can add additional kTC noise and PRNU (photo-response non-uniformity) to the image sensor 5. Finally, the source follower settling time when selected can be quite prolonged due to low loop-gain and small source follower gain. This long settling time can both make the source follower transistor 14 subject to RTS (e.g., 1/f) noise as well as increase the row readout time causing lower frame rates. The RTS noise is typically caused by traps in the oxide under the source follower transistor 14. The RTS noise gets worse the longer the source follower transistor is amplifying a signal. If the pixel output settling time can be reduced, the RTS noise will improve dramatically.
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip 2 that includes an array of pixels 10 and a controller 23 that provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M-by-N pixels, with the size of the array 5 depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 23 selects a particular row of pixels in the array 5 by controlling the operation of row addressing circuit 21—the vertical addressing circuit—and row drivers 22. Charge signals stored in the selected row of pixels are provided on the column lines 17 (FIG. 1) to a readout circuit 25 in the manner described above. The pixel signals (reset voltage Vrst and image signal voltage Vsig) read from each of the columns can then be read out, sampled and held, subtracted (Vrst−Vsig) and the result sequentially sent to further processing such as digitization, using a column addressing circuit. Differential pixel signals (Vrst, Vsig) corresponding to the readout reset signal (Vrst) and image signal (Vsig) are provided as respective outputs Vout1, Vout2 of the readout circuit 25 for subtraction and subsequent processing. Alternatively, readout circuit 25 provides a combined differential signal of the two signals Vrst, Vsig.
As noted, the source follower transistor 14 limits output swing available for the pixel output signals, where the gain maybe limited to 0.8 of the signal applied to input gate of the source follower transistor, it would be desirable to increase the gain applied to pixel output signals.